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APLUS
MAKE YOUR PRODUCTION A-PLUS
AVXX32E -A SERIES DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Sales E-mail: sales@aplusinc.com.tw Technology E-mail: service@aplusinc.com.tw
Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw
AVXX32E -A SERIES
3, 7, 14 Seconds Complicate Pure Speech
Features
Operating voltage: 2.4V~5.0V One single-key can implement play-all, play-next and random function. Maximum play count is 16. Each input can implement looping function. Single-key input can be last-key priority for stand-alone input or first-key priority. Each input trigger can select trigger mode: (For OKY, TG0, TG1, TG3) Edge/Level, Hold/Unhold, Retrigger/Irretrigger. Each input trigger can select its own debounce time: Fast debounce: < 200us; Slow debounce: ~16ms (S.R.=6.0kHz) Support bouncing trigger solution for retrigger application. (Second trigger force to retrigger and slow debounce.) Maximum table entries are 204*4. Word count is only limited by ROM capacity. 3 output ports for Status or LED application: OP_A Status: Busy_high, DC_low, Stop_high,DC_high LED: +Fast,+Slow, Dyn(7/10), Off OP_B Status: Busy_high, DC_low, Stop_high, DC_high LED: -Fast, -Slow, Dyn(9/10), On OP_C Status: Busy_high, DC_low, Busy_low, DC_high LED: +Fast, +Slow, On, Off Each output can specify its initial state (High or Low) Outputs can be set as constant current regardless of the supply voltage varied. Two PWM playing ports. Drive speaker or buzzer directly. Body define: 3, 7, 14 seconds. (Total ROM size : 18k,42k,84k) voice length(3s body:16384*5,7s body:40960*5,14s body:83968*5) Voice algorithm: 5-bits LOG_PCM External resister for system frequency Sixteen default sampling frequencies are supported. The default frequencies can be changed by applying an external resistor. Support single key play on/off. (For OKY, TG0, TG1) Programmable only pull-low input. (For OKY,TG3) Programmable pull-high, pull-low or floating input. (For TG0,TG1) TG3_OPC pin can option as input or output by mask option
General Description
The AVXX32E -A are series of single-chip synthesizing CMOS VLSI IC which synthesizes voice by LOG_PCM algorithm. Table programming and shared multiple I/O pins make the applications flexible. Powerful functions and pure speech architecture make the AVXX32E -A series are able to best fit most speech applications and a best cost/performance ratio as a result. The programming of the AVXX32E -A series is first to define words. Each word contains voice data (or mute length), output method, assemble the words into sentences first, and then the programmer can assign the sentences to the keys corresponding to the user inputs. The TG3_OPC pin of the AVXX32E -A series is multiplexed. This means it can option as input pin or output pin.
Body Option Table
Body AV0332E AV0732E AV1432E ROM 84K 42K 18K Table D0 - 3FF D0 - 2FF D0 - 1FF KEY OKY, TG0 - TG1 & TG3 OKY, TG0 - TG1 & TG3 OKY, TG0, TG3 OUT OPA, OPB, OPC OPA, OPB, OPC OPA, OPC
Preliminary
9-1
Ver. 0.1
AVXX32E -A SERIES
Pin Description
Pin Name VDD TEST OSC OKY TG0, TG1 TG3_OPC OPB OPA PWM1, PWM2 VSS I/O Power In In In In In Out Out Out Out Power Description Positive power supply Test enable pad, high-active, pull-low With resister connected to VDD for system clock generating Trigger input, active-high, with internal pull_low resistor. Can define as sequential key or random key. Trigger input, active-high with internal pull_low resistor. Trigger input, active-high Status output Status output Status output Voltage output to drive speaker or buzzer Negative power supply
Absolute Maximum Rating
Symbol VDD~VSS VIN (for input) VOUT (for all outputs) T (operating) T (storage) Rating -0.5 ~ +0.5 VSS-0.3 < VIN < VDD+0.3 VSS < VOUT < VDD -10 ~ +60 -55 ~ +125 Unit V V V
DC Characteristics
Symbol VDD Isb Iop IOL Ioh d F/F Parameter Min Typ. Max Unit Condition Operating Voltage 2.4 3.0 5.0 V A VDD=3.0V, I/O open Standby 1 Supply Current A VDD=3.0V, No loading Operating 400 OPA, OPB source Current -20 mA VDD=3.0V, VIP=2.7V OPA, OPB sink Current 20 mA VDD=3.0V, VOP=0.3V VDD=4.5V Frequency Variation by diff. 10 % lot fOSC =384kHz
Function Diagram
1. OPA/B/C (1:0) are the output options. Output OPA Option Status LED OPB Status LED OPC Status LED 0(00) BH +Fast BH -Fast BH +Fast 1(01) DL +Slow DL -Slow DL +Slow 2(10) SH Dy07 SH Dy09 BL ON 3(11) DH OFF DH ON DH OFF
Status output mode: SH: Single pulse output, hi-level output BH: Busy output, hi-level output
Preliminary
9-2
Ver. 0.1
AVXX32E -A SERIES
BL: Busy output, lo-level output DH: Always Hi-level output DL: Always Lo-level output LED output mode: +Fast, -Fast: High frequency alternate output +Slow, -Slow: Low frequency alternate output Dy09: Volume level (9/10)output control. If code > 9/10(FFh), then output "Lo". Otherwise output "Hi" Dy07: Volume level (7/10)output control. If code > 7/10(FFh), then output "Lo". Otherwise output "Hi" ON : Always Lo-level output OFF: Always Hi-level output Note: The Status and LED mode is optioned by mask option. Edge/Level mode (If sentence = word1+word2) Edge mode Trigger length > Voice length
TG
Audio
word1 word2 debounce time
Trigger length < Voice length
TG word1 word2 debounce time
Level mode Trigger length > Voice length (if sentence=word1+word2)
TG
Audio
word1 word2 word3 word4 debounce time
Trigger length < Voice length (if sentence = word1+word2)
TG
Audio
word1 word2 debounce time
Preliminary
9-3
Ver. 0.1
AVXX32E -A SERIES
Hold/Unhold mode (If sentence = word1+word2) Hold mode
TG word2 Audio word1 debounce time
Unhold mode
TG
Audio
word1 word2 debounce time
Retrigger/Irretrigger mode (If sentence = word1+word2) Retrigger mode (Edge Unhold mode)
TG
Audio
word1
word2
word3 word4
debounce time
Irretrigger mode (Edge, Unhold mode)
TG
Audio
word1 word2 debounce time
Last key priority If TG1, TG3 are retrigger mode
Looping function If sentence is set to looping mode (sentence1_sentence2)
Preliminary
9-4
Ver. 0.1
AVXX32E -A SERIES
Unhold mode
TG Audio
sentence1 sentence2 sentence2 sentence2
Hold mode
TG
sentence2
Audio
sentence1 sentence2
Force to retrigger and slow debounce option (Trigger mode set to Fast debounce and Irretrigger mode)
1st TG FRSB Audio
Don't care W11 W12 W13 W14
This word must be larger than glitch period. (A mute word can be used berhaps.)
2nd TG FRSB Audio
Slow debounce, Retrigger mode W21 W22 W23 W24
Slow debounce, Retrigger mode Fast debounce, Irretrigger mode
Fast debounce, Irretrigger mode
Busy=0, FRSB set to high; Busy=1, depending on FRSB setting. If FRSB=0, force to slow debounce and retrigger mode; If FRSB=1, no change (fast debounce and irretrigger mode). Stand-alone trigger inputs are enabled at the same time
OKY TG0 TG1 TG3
Audio
This voice is enabled by TG3
Preliminary
9-5
Ver. 0.1
AVXX32E -A SERIES
Trigger input priority is TG3 > TG1 > TG0 > OKY
Application circuit
External resister, Driver speaker by PWM, driver LED
ROSC=200k Direct Keys
for frequency option 8
Preliminary
9-6
Ver. 0.1
AVXX32E -A SERIES
Pad Diagram & Pad Location (1) AV0332E
Note: The IC substrate should be connect to VSS
Pad No. 1 2 3 4 5
Pad Name PAD_OSC PAD_OKY PAD_OPA PAD_TG3OPC PAD_TEST
X(um) 108.75 356.2 586.1 777.4 1007.3
Y(um) 214.05 94.05 94.05 94.05 94.05
Pad No. 6 7 8 9 10
Pad Name PAD_TG0 VDD PAD_PWM2 PAD_PWM1
X(um) 1281.1 1302.8 1101.9 681.1
Y(um) 94.05 595.6 595.6 595.6
VSS 480.2 595.6 Chip size : 1387.9 x 696.6 ( m)2
Preliminary
9-7
Ver. 0.1
AVXX32E -A SERIES
(2) AV0732E
Note: The IC substrate should be connect to VSS Pad No. 1 2 3 4 5 6 Pad Name PAD_OSC PAD_OKY PAD_OPA PAD_OPB PAD_TG3OPC PAD_TEST X(um) 108.75 108.75 291.65 573.45 764.75 994.65 Y(um) 214.05 94.05 94.05 94.05 94.05 94.05 Pad No. 7 8 9 10 11 12 Pad Name PAD_TG1 PAD_TG0 VDD PAD_PWM2 PAD_PWM1 X(um) 1279.15 1279.15 1302.8 1101.9 681.1 Y(um) 94.05 214.05 722.3 722.3 722.3
VSS 480.2 722.3 Chip size : 1387.9 x 823.3 ( m)2
Preliminary
9-8
Ver. 0.1
AVXX32E -A SERIES
(3)AV1432E
Note: The IC substrate should be connect to VSS Pad No. 1 2 3 4 5 6 Pad Name PAD_OSC PAD_OKY PAD_OPA PAD_OPB PAD_TG3OPC PAD_TEST X(um) 108.75 108.75 291.65 573.45 764.75 994.65 Y(um) 214.1 94.05 94.05 94.05 94.05 94.05 Pad No. 7 8 9 10 11 12 Pad Name PAD_TG1 PAD_TG0 VDD PAD_PWM2 PAD_PWM1 VSS X(um) 1279.2 1279.2 1302.8 1101.9 681.1 Y(um) 94.05 214.1 867 867 867
480.2 867 Chip size : 1387.9 x 968 ( m)2
Preliminary
9-9
Ver. 0.1

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